Semiconductor device

ABSTRACT

A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims benefit of priority under 35USC §119 toJapanese patent application No. 2002-178250, filed on Jun. 19, 2002, thecontents of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device, forexample, a power semiconductor device which realizes a lowon-resistance.

[0004] 2. Related Background Art

[0005] In recent years, an insulated gate bipolar transistor (IGBT) hasbroadly been used as a power semiconductor device which has a breakdownvoltage of 600 V or more. Since this power semiconductor device isgenerally used as a switch, a low on-resistance and a high switchingrate are requested.

[0006] An IGBT according to a conventional art will be described withreference to FIGS. 27 and 29. It is to be noted that in drawingsdescribed later, the same components are denoted with the same referencenumerals, and the detailed description thereof is appropriately omitted.

[0007]FIG. 27 is a sectional view schematically showing one example ofthe IGBT comprising a trench gate structure which has recently been usedbroadly. An IGBT 110 shown in the figure comprises an n⁻-type base layer142, a p⁺-type emitter layer 44, a collector electrode 56, p-type welllayers 160, n⁺-type source layers 148, an emitter electrode 158, gateoxide films 52, and a gate electrode 54. The p⁺-type emitter layer 44 isformed on the undersurface of the n⁻-type base layer 142 on the lowerside in the sheet of the figure, and the collector electrode 56 isdisposed in contact with the p⁺-type emitter layer 44. The p-type welllayer 160 is formed in the upper surface of the n⁻-type base layer 142in the sheet of the figure. A trench TRa is selectively formed halfwayin the depth of the n⁻-type base layer 142 from the surface of thep-type well layer 160 through the p-type well layer 160, and the gateelectrode 54 is disposed via the gate oxide film 52 in the trench. Inthe n⁻-type base layer 142, a width 2 a of an active region held betweenthe gate oxide films 52 is usually, for example, 2 a≅4 μm. The n⁺-typesource layer 148 is selectively formed in contact with a trench TR52 inthe surface portion of the p-type well layer 160. Furthermore, theemitter electrode 158 is disposed so as to extend to the surface of then⁺-type source layer 148 from the upper surface of the p-type well layer160, thereby the emitter electrode 158 contacts the p-typewell layer 160and n⁺-type source layer 148.

[0008] An operation of the IGBT 110 shown in FIG. 27 is as follows.

[0009] When a bias voltage which is positive with respect to the emitterelectrode 158 is applied to the gate electrode 54, an inversion layer isgenerated in the p-type well layer 160 in a region in the vicinity ofthe outer surface of the gate oxide film 52, and electrons are injectedinto the n⁻-type base layer 142. Accordingly, a positive hole isinjected into the n⁻-type base layer 142 from the p⁺-type emitter layer44, which turns the IGBT 110 on. The positive hole injected at this timeruns in the n⁻-type base layer 142 to flow into the p-type well layer160.

[0010] However, the related-art IGBT 110 shown in FIG. 27 has thefollowing two problems.

[0011] A first problem is that, due to the positive hole flowing intothe p-type well layer 160, accumulation of the positive hole decreasesin the vicinity of an interface between the n⁻-type base layer 142 andthe p-type well layer 160, and carriers are reduced. As a result, theon-resistance of the device increases.

[0012] A second problem is a drop in destruction tolerance by aso-called latch up phenomenon. Specifically, when the IGBT 110 is turnedoff, a potential of the p-type well layer 160 may rise by apositive-hole current discharged through the p-type well layer 160, andthe destruction tolerance of the IGBT 110 may drop by the electronsinjected into the p-type well layer 160 from the n⁺-type source layer148. This is because with the increase of a breaking current, thepositive-hole current flowing right under the n⁺-type source layer 148increases.

[0013] To solve the first problem, the use of the Injection Enhancement(IE) effect has been known in which an n-type impurity layer is formedin a lower part of the p-type well layer 160 to increase an accumulatedamount of the positive hole and to reduce the on-resistance. However,when the n-type impurity layer is formed in the lower part of the p-typewell layer 160, a breakdown voltage of the device itself isdeteriorated. Thus, there is a limitation in raising a density of then-type impurity layer. For the limit value, for example, an impuritytotal amount is in a range of about 1 to 2×10¹² cm⁻², and the density isin a range of about 10¹⁴ to 10¹⁵ cm⁻³. Therefore, there is a limitationin reduction of the on-resistance by the n-type impurity layer disposedin the lower part of the p-type well layer 160, and the on-resistancecannot be sufficiently lowered as that in a thyristor.

[0014] It is known that another means for solving the first problemcomprises: further disposing dummy trenches TRd, which has no relationwith the operation of the device, between active trenches TRa whichcontribute to the operation of the device, for example, as in an IGBT120 shown in FIG. 28; and forming an oxide film 162 in the surface ofthe semiconductor layer between the dummy trenches TRd. Since thisconstitution interrupts contact of the semiconductor layer between thedummy trenches TRd with an emitter electrode 58, the resistanceincreases in discharging the positive hole to the emitter electrode 58from an n⁻-type base layer 42. As a result, the accumulated amount ofthe positive hole can be increased. It is to be noted that to controlthe injection of the positive hole into the n⁻-type base layer 42 fromthe p⁺-type emitter layer 44 in the IGBT 120 shown in FIG. 28, an n-typebuffer layer 66 is inserted between these layers. To reduce an inputcapacity, dummy electrodes 154 in the dummy trenches TRd having nocontact with a current passage are connected to the emitter electrode58.

[0015] However, according to researches of the present inventors, in theconstitution shown in FIG. 28, a surface recombination occurs in aninterface portion shown by a dot line DL between the n⁻-type base layer42 and a dummy gate oxide film 172. Since the accumulated amount of thepositive hole drops accordingly, it has been found out to be difficultto reduce the on-resistance.

[0016] As described above, the related-art IGBT comprising thetrenchgate structure has both the first problem that it is difficult toreduce the on-resistance and the second problem that with the increaseof the breaking current, the positive-hole current flowing through thep-type well increases and the device may be destroyed.

BRIEF SUMMARY OF THE INVENTION

[0017] According to a first aspect of the present invention, there isprovided a semiconductor device comprising: a base layer of a firstconductivity type; a barrier layer of a first conductivity type formedon the base layer; a trench formed from the surface of the barrier layerto such a depth as to reach a region in the vicinity of an interfacebetween the barrier layer and the base layer; a gate electrode formed inthe trench via a gate insulating film; a contact layer of a secondconductivity type selectively formed in a surface portion of the barrierlayer; a source layer of the first conductivity type selectively formedin the surface portion of the barrier layer so as to contact the contactlayer and a side wall of the gate insulating film in the trench; and afirst main electrode formed so as to contact the contact layer and thesource layer.

[0018] According to a second aspect of the present invention, there isprovided a semiconductor device comprising: a base layer of a firstconductivity type; a barrier layer of the first conductivity type formedabove the base layer; a trench formed from the surface of the barrierlayer to such a depth as to reach a region in the vicinity of aninterface between the barrier layer and the base layer; a gate electrodeformed in the trench via a gate insulating film; a contact layer of asecond conductivity type selectively formed in a surface portion of thebarrier layer; a source layer of the first conductivity type selectivelyformed in the surface portion of the barrier layer so as to contact aside wall of the gate insulating film in the trench and the contactlayer; a well layer of the second conductivity type formed between thecontact layer and the source layer, and the barrier layer; and a firstmain electrode formed so as to contact the contact layer and the sourcelayer, wherein the region between the trenches includes a dummy regionhaving no relation to the operation of the device other than an activeregion for a current path.

[0019] According to a third aspect of the present invention, there isprovided a semiconductor device comprising: a base layer of a firstconductivity type; a barrier layer of the first conductivity type formedon the base layer; a well layer of a second conductivity type formed onthe barrier layer; a trench formed from the surface of the well layer tosuch a depth as to reach a region in the vicinity of an junction surfacebetween the barrier layer and the base layer; a gate electrode formed inthe trench via a gate insulating film; a contact layer of the secondconductivity type selectively formed in a surface portion of the welllayer; a source layer of the first conductivity type selectively formedin the surface portion of the well layer so as to contact a side wall ofthe gate insulating film in the trench and the contact layer; and afirst main electrode formed so as to contact the contact layer and thesource layer, wherein assuming that a total sum of impurity densities inthe region of the barrier layer between the trenches is Qn, the Qn has arelation of the following equation:

Qn≧2×10¹² cm⁻².

[0020] According to a fourth aspect of the present invention, there isprovided a semiconductor device comprising: a base layer of a firstconductivity type; a well layer of a second conductivity type formed onthe base layer; an active trench formed from the surface of the welllayer to such a depth as to reach the inside of the base layer so as tosandwich an active region to form a current path in the well layer; adummy trench formed in the region excluding the active region of thewell layer from the surface of the well layer to such a depth as toreach the inside of the base layer; a gate electrode formed in theactive trench via a gate insulating film; a dummy electrode formed inthe dummy trench via the gate insulating film; a source layer of thefirst conductivity type selectively formed in a surface portion of theactive region of the well layer so as to contact a side wall of the gateinsulating film in the active trench; and a first main electrode formedso as to contact at least the well layer and the source layer, whereinthe dummy electrode in the dummy trench disposed adjacent to the activetrench is electrically connected to the gate electrode, and the dummyelectrode other than that of the dummy trench disposed adjacent to theactive trench is electrically connected to the first main electrode.

[0021] According to a fifth aspect of the present invention, there isprovided a semiconductor device comprising: a base layer of a firstconductivity type; a well layer of a second conductivity type formed onthe base layer; an active trench formed from the surface of the welllayer to such a depth as to reach the inside of the base layer so as tosandwich an active region for a current path in the well layer; a dummytrench formed in the region excluding the active region of the welllayer from the surface of the well layer to such a depth as to reach theinside of the base layer; a gate electrode formed in the active trenchvia a first gate insulating film; a dummy electrode formed in the dummytrench via a second gate insulating film; a source layer of the firstconductivity type selectively formed in a surface portion of the welllayer in the active region so as to contact a side wall of the gateinsulating film in the active trench; and a first main electrode formedso as to contact the well layer and the source layer, wherein a distancebetween the dummy trench disposed adjacent to the active trench, and theactive trench is shorter than that between the dummy trenches.

[0022] According to a sixth aspect of the present invention, there isprovided a semiconductor device comprising: a base layer of a firstconductivity type; a well layer of a second conductivity typeselectively formed on an active region for a current path of the baselayer; a diverter layer of the second conductivity type selectivelyformed in a region of the base layer excluding the active region; afirst trench formed from the surface of the well layer to such a depthas to reach the inside of the base layer; a second trench formed fromthe surface of the diverter layer to such a depth as to reach the insideof the base layer; gate electrodes formed in the first and secondtrenches via insulating films; a source layer of the first conductivitytype selectively formed in a surface portion of the active region of thewell layer so as to contact a side wall of the gate insulating film inthe first trench,; and a first main electrode electrically connected tothe well layer, the source layer and the diverter layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a sectional view showing a schematic constitution of afirst embodiment of a semiconductor device according to the presentinvention;

[0024]FIGS. 2A to 2E are explanatory views of the detailed constitutionand operation principle of the IGBT shown in FIG. 1;

[0025]FIG. 3 is a sectional view showing the schematic constitution of asecond embodiment of the semiconductor device according to the presentinvention;

[0026]FIGS. 4A and 4B are explanatory views showing a reason why thebreakdown voltage of a device does not drop, when a width of an activeregion is decreased but even when a density of an n-type barrier layeris increased;

[0027]FIG. 5 is a table showing a capability of the IGBT shown in FIG. 3in comparison with that of the IGBT according to a related art;

[0028]FIG. 6 is a sectional view showing the schematic constitution of athird embodiment of the semiconductor device according to the presentinvention;

[0029]FIG. 7 is a sectional view showing the schematic constitution of afourth embodiment of the semiconductor device according to the presentinvention;

[0030]FIG. 8 is a partial perspective view showing the schematicconstitution of a fifth embodiment of the semiconductor device accordingto the present invention;

[0031]FIG. 9 is a plan view showing a main part of a sixth embodiment ofthe semiconductor device according to the present invention;

[0032]FIG. 10 is a plan view showing the main part of a seventhembodiment of the semiconductor device according to the presentinvention;

[0033]FIG. 11 is a sectional view showing the schematic constitution ofan eighth embodiment of the semiconductor device according to thepresent invention;

[0034]FIG. 12 is a sectional view showing the schematic constitution ofa ninth embodiment of the semiconductor device according to the presentinvention;

[0035]FIG. 13 is a sectional view showing the schematic constitution ofa tenth eighth embodiment of the semiconductor device according to thepresent invention;

[0036]FIG. 14 is a schematic sectional view showing a modificationexample of the semiconductor device shown in FIG. 13;

[0037]FIG. 15 is a sectional view showing the schematic constitution ofan eleventh embodiment of the semiconductor device according to thepresent invention;

[0038]FIG. 16 is a sectional view showing the schematic constitution ofa twelfth embodiment of the semiconductor device according to thepresent invention;

[0039]FIG. 17 is a schematic sectional view showing a modificationexample of the semiconductor device shown in FIG. 16;

[0040]FIG. 18 is a sectional view showing the schematic constitution ofa thirteenth embodiment of the semiconductor device according to thepresent invention;

[0041]FIG. 19 is a schematic sectional view showing a modificationexample of the semiconductor device shown in FIG. 18;

[0042]FIGS. 20A and 20B are explanatory views of an operation of thesemiconductor device shown in FIG. 18;

[0043]FIG. 21 is a sectional view showing the schematic constitution ofa fourteenth embodiment of the semiconductor device according to thepresent invention;

[0044]FIG. 22 is a sectional view showing the schematic constitution ofa fifteenth embodiment of the semiconductor device according to thepresent invention;

[0045]FIG. 23 is a sectional view showing the schematic constitution ofa sixteenth embodiment of the semiconductor device according to thepresent invention;

[0046]FIG. 24 is a sectional view showing the schematic constitution ofa seventeenth embodiment of the semiconductor device according to thepresent invention;

[0047]FIG. 25 is a sectional view showing the schematic constitution ofan eighteenth embodiment of the semiconductor device according to thepresent invention;

[0048]FIG. 26 is a sectional view showing the schematic constitution ofa nineteenth embodiment of the semiconductor device according to thepresent invention;

[0049]FIG. 27 is a schematic sectional view showing one example of theIGBT according to a related art; and

[0050]FIG. 28 is a schematic sectional view showing another example ofthe IGBT according to the related art.

DETAILED DESCRIPTION OF THE INVENTION

[0051] Some embodiments of the present invention will be describedhereinafter with reference to the drawings. It is to be noted that IGBTscomprising vertical and horizontal trench gate structures will mainly bedescribed hereinafter. However, the present invention is not limited tothese semiconductor devices, and can be applied to other semiconductordevices, for example to general power semiconductor devices comprisingtrench MOS gate structures such as a vertical trench MOSFET andhorizontal trench MOSFET. In the following embodiments, a firstconductivity type is defined as an n-type and a second conductivity typeis defined as a p-type.

[0052] (1) First Embodiment

[0053]FIG. 1 is a sectional view showing a schematic constitution of afirst embodiment of a semiconductor device according to the presentinvention. As apparent from comparison with FIG. 27, characteristics ofa semiconductor device 2 of the present embodiment lie in that a p-typewell layer (see FIG. 27, reference numeral 160) is not disposed in thedevice 2 and that the width 2 a of the active region in the n⁻-type baselayer 42 is formed to be smaller than that of the IGBT 110 of FIG. 27.In a region between the n⁺-type source layers 48, a p⁺-type contactlayer 50 is formed. In the active region between trenches TRa, an n-typebarrier layer 46 having an impurity concentration higher than that ofthe n⁻-type base layer 42 contacts the p⁺-type contact layer 50 and then⁺-type source layers 48 on the upper surface thereof. Furthermore, then-type barrier layer 42 is formed so that the undersurface thereofreaches a depth which substantially corresponds to that of theundersurfaces of the gate electrodes 54. The width 2 a of the activeregion is, for example, about 2 μm or less in the present embodiment,and this value is about the half or less of that of the related-artIGBT. The other structure of the semiconductor device 2 of the presentembodiment is substantially the same as that of the IGBT 110 shown inFIG. 27.

[0054] Detailed constitution and operation principle of thesemiconductor device 2 shown in FIG. 1 will be described with referenceto FIGS. 2A to 2E. FIG. 2A shows only a device sectional structure of anupper part of the semiconductor device 2 shown in FIG. 1. FIG. 2B is aschematic view of a potential of a portion cut along line A-A of FIG.2A. Furthermore, FIGS. 2C to 2E show examples of concentrationdistributions of the n-type barrier layer 46 and n⁻-type base layer 42.

[0055] A code E_(F) shown in FIG. 2B represents Fermi level. The Fermilevel E_(F) shown in FIG. 2B is obtained using a p-type polysilicon as amaterial of the gate electrode 54. By this potential structure, then-type barrier layer 46 is depleted. Therefore, even when a gate voltageis not applied, the device obtains a forward direction inhibitive state.At this time, density N_(BAR) of the n-type barrier layer 46substantially has the following relation with a i.e. the half width ofthe active region.

1×10¹² cm⁻² ≈N _(BAR) cm⁻³ ×a cm   Equation (1)

[0056] For example, when a=1×10⁻⁴ cm (1 μm), N_(BAR)=1×10¹⁶ cm⁻³, theobtained density is 100 or more times a usual density of the n⁻-typebase layer 42.

[0057] The operation of the semiconductor device 2 of the presentembodiment is as follows. First, when a bias voltage having a positivedirection with respect to the emitter electrode 58 is applied to thegate electrodes 54, a potential shown in FIG. 2B is lowered, andelectrons are injected into the n⁻-type base layer 42 from the n⁺-typesource layers 48 via the n-type barrier layer 46. The p⁺-type emitterlayer 44 is thus biased in the positive direction with respect to then⁻-type base layer 42, a positive hole is injected into the n⁻-type baselayer 42 from the p⁺-type emitter layer 44, and the device is therebybrought into an on-state. The positive hole injected at this time runsthrough the n⁻-type base layer 42 and further flows into the n-typebarrier layer 46. At this time, since the density N_(BAR) of the n-typebarrier layer 46 is high as described above, the positive hole canhardly flow into the p⁺-type contact layer 50. Therefore, accumulationof the positive hole occurs in the vicinity of a junction surfacebetween the n⁻-type base layer 42 and the n-type barrier layer 46. As aresult, the amount of carriers increases and the on-resistance drops.

[0058] Further as shown in FIG. 2D, the concentration distribution ofthe n-type barrier layer 46 may have a gradient, which distribution ismore effective. On the contrary, when a converse gradient as shown inFIG. 2E is provided to the concentration distribution, manufacture ofthe device is facilitated since a diffusion step from the surface can beused.

[0059] (2) Second Embodiment

[0060]FIG. 3 is a sectional view showing the schematic constitution of asecond embodiment of the semiconductor device according to the presentinvention. As apparent from the comparison with FIG. 1, thecharacteristics of an IGBT 4 of the present embodiment lie in a p-typewell layer 60 is disposed between the n⁺-type source layers 48 and ap⁺-type contact layer 58, and the n-type barrier layer 46.

[0061] With regard to the IGBT 4 of the embodiment, when the width ofthe active region is reduced, the breakdown voltage of the device doesnot drop even when the density N of the n-type barrier layer 46 israised. A reason for this will be described with reference to FIGS. 4Aand 4B. FIG. 4A is a partial sectional view along line B-B of FIG. 3.FIG. 4B is an electric field distribution diagram along line B-B of FIG.3. When the amount a the half of the interval between the trenches TRais large, as shown by a broken line EL_(W) of FIG. 4B, an electric fieldtakes a peak value in the pn-junction between the p-type well layer 60and the n-type barrier layer 46. On the other hand, when the amount athe half of the interval between the trenches TRa is reduced to depletethe n-type barrier layer 46, as shown by a solid line EL_(N) of FIG. 4B,the peak value of the electric field moves to bottom portions of thetrenches TRa. Therefore, even when the concentration of the n-typebarrier layer 46 is raised, the breakdown voltage does not drop.

[0062] Other advantages of the IGBT 4 of the present embodiment will bedescribed with reference to FIG. 5. FIG. 5 is a table showing acapability of the IGBT 4 based on an experiment result in comparisonwith that of the IGBT according to a related art. It is to be noted thatin the figure Qn represents a total sum of an impurity concentration inan n-type impurity region between the trenches TRa.

[0063] As shown in Example 1 in upper second line of the table in FIG.5, when Qn is increased in the IGBT 4 of the present embodiment, anon-voltage lowers as compared with a structure example according to therelated art. However, when the amount a the half of the trench intervalremains to be large (a=2 μm) in the same manner as in the related art,the breakdown voltage is deteriorated.

[0064] On the other hand, when the amount a the half of the trenchinterval is reduced (a=1 μm) in Examples 2 and 3 of the IGBT 4 of thepresent embodiment, even with the large Qn, the on-voltage can belowered without deteriorating the breakdown voltage. This has alsorevealed that the amount a the half of the width of the active regionand the total sum Qn of the impurity densities of the n-type impuritylayers in the active region are preferably in the following range.

a≦1 μm and/or Qn≧2×10¹² cm⁻²   Equation (2)

[0065] (3) Third Embodiment

[0066]FIG. 6 is a sectional view showing the schematic constitution of athird embodiment of the semiconductor device according to the presentinvention. The characteristics of an IGBT 6 shown in the figure lie inthat an n-type barrier layer 47 in the active region extends to a regiondeeper than the bottom surface of the trench TRa. The other constitutionof the IGBT 6 is substantially the same as that of the IGBT 4 shown inFIG. 3. When the n-type barrier layer 47 is formed so as to extenddeeper than the bottom surface of the trench as in the presentembodiment, the positive hole is rendered not to flow in an interfaceportion between the barrier layer 47 and the oxide film 52. Theabove-described problem that the accumulated amount of the positiveholes drops due to the surface recombination can also be solved and theon-resistance can further be reduced.

[0067] (4) Fourth Embodiment

[0068]FIG. 7 is a sectional view showing the schematic constitution of afourth embodiment of the semiconductor device according to the presentinvention. As shown in the figure, the characteristics of an IGBT 8 ofthe present embodiment lie in that the IGBT further comprises an n-typebuffer layer 62 disposed between the n⁻-type base layer 42 and thep⁺-type emitter layer 44. As the n-type buffer layer 62 is thusdisposed, the breakdown voltage of the device can be prevented fromdropping even when the n⁻-type base layer 42 is thinned in order tolower the on-resistance.

[0069] (5) Fifth Embodiment

[0070]FIG. 8 is a partial perspective view showing the schematicconstitution of a fifth embodiment of the semiconductor device accordingto the present invention. The characteristics of an IGBT 10 shown in thefigure lie in that the n⁺-type source layers 48 and the p⁺-type contactlayers 50 are alternately disposed in a striped plane shape along thedirection of the trench TRa in a region between the trenches TRa in aview. The other constitution of the IGBT 10 is substantially the same asthat of the IGBT 4 shown in FIG. 3.

[0071] (6) Sixth Embodiment

[0072]FIG. 9 is a plan view showing a main part of a sixth embodiment ofthe semiconductor device according to the present invention. In thefigure, an emitter electrode is omitted. The characteristics of an IGBT12 of the present embodiment lie in a cell arrangement of a matrixshape. First, the trenches TRa are disposed so that the gate oxide film52 forms a lattice shape in the plane view. Next, the n⁺-type sourcelayer 48 is disposed around the p⁺-type contact layer 50 disposed in themiddle in each lattice. The other constitution of the IGBT 12 issubstantially the same as that of the IGBT 4 shown in FIG. 3.

[0073] (7) Seventh Embodiment

[0074]FIG. 10 is a plan view showing the main part of a seventhembodiment of the semiconductor device according to the presentinvention. Also in this figure, the emitter electrode is omitted. Thecharacteristics of an IGBT 14 of the present embodiment also lie in amode of the cell arrangement. Assuming that a left/right direction inthe sheet of the figure is a row direction and a vertical direction inthe sheet of the figure is a column direction, cells are arranged sothat columns disposed adjacent to each other alternately shift in thecolumn direction about by a half of a cell pitch of the columndirection. In the same manner as in the IGBT 12 of FIG. 9, the p⁺-typecontact layer 50 is disposed in the middle in each lattice, and then⁺-type source layer 48 is disposed around the p⁺-type contact layer 50in the plane view. The other constitution of the IGBT 14 issubstantially the same as that of the IGBT 4 shown in FIG. 3.

[0075] (8) Eighth Embodiment

[0076]FIG. 11 is a sectional view showing the schematic constitution ofan eighth embodiment of the semiconductor device according to thepresent invention. The characteristics of an IGBT 16 shown in the figurelie in that an insulating film 64 is disposed on a surface of a portion(dummy region) which does not contribute to the operation of the devicein the region between the trenches TRa to prevent the dummy region fromcontacting the emitter electrode. Therefore, an emitter electrode 58 isformed from the region of the p⁺-type contact layer 50 in a portion of afunction cell (active region) to a region on the gate oxide films 52sandwiching the active regions through the region of the n⁺-type sourcelayers 48. Furthermore, the emitter electrode is also formed so as tocover the insulating film 64 so that emitter contacts of the functioncells disposed adjacent to each other are connected to each other. Whena channel region is thinned in this manner, the on-voltage of the devicefurther drops. It is to be noted that in the present embodiment thedummy region includes a structure similar to that of the active region.However, the structure of the dummy region is not limited to this, andmay also be the n-type barrier layer 46 as such or may also include astructure only of p-layers as long as contact with the emitter electrodeis interrupted.

[0077] (9) Ninth Embodiment

[0078]FIG. 12 is a sectional view showing the schematic constitution ofa ninth embodiment of the semiconductor device according to the presentinvention. As apparent from the comparison with FIG. 28, thecharacteristics of an IGBT 18 shown in the figure lie in that, of dummytrenches TRd1 through TRd3, electrodes in dummy trenches TRd1 and TRd3positioned adjacent to active trenches TRa1, TRa2 contacting a currentpath, respectively, are connected to a gate electrode G. The width ofthe active region held between the active trenches is about 2 μm or lessin the same manner as in the first embodiment. The other constitution ofthe IGBT 18 is substantially the same as that of the IGBT 120 shown inFIG. 28.

[0079] According to the IGBT 18 of the present embodiment, in theon-state of the device, the gate electrode G is biased in the positivedirection with respect to the voltage of the emitter electrode 58 bythis constitution. Therefore, electrons are accumulated in theinterfaces between the gate oxide films 52 of the dummy trenches TRd1,TRd3 and the n⁻-type base layers 42. The carriers in the surfaces of thedummy trenches TRd1 and TRd3 can be prevented from being recombined, andthe carrier density in the n⁻-type baselayer 42 can be raised. As aresult, conductivity loss of the IGBT 18 is reduced.

[0080] (10) Tenth Embodiment

[0081]FIG. 13 is a sectional view showing the schematic constitution ofa tenth eighth embodiment of the semiconductor device according to thepresent invention. An IGBT 20 shown in the figure is different from theIGBT 18 shown in FIG. 12 in that an n-type barrier layer 70 is disposedso as to be inserted between the p⁺-type contact layer 50 and p-typewell layer 51, and the n⁻-type base layer 42. When the n-type barrierlayer 70 is inserted/disposed in this position, resistance furtherincreases in discharging the positive hole to the emitter electrode 58from the n⁻-type base layer 42. As a result, since the accumulatedamount of the positive hole can be increased, the conductive loss canfurther be reduced. Even in the present embodiment, the impurityconcentration of the n-type barrier layer 70 is higher than that of then⁻-type base layer 42 at least in the vicinity of the interface betweenthe n-type barrier layer 70 and the n⁻-type base layer 42. Furthermore,in the IGBT 20 of the present embodiment, in order to prevent thebreakdown voltage from being deteriorated, each distance between thetrenches is preferably 2 μm or less as described in the secondembodiment.

[0082] A modification example of the present embodiment is shown in FIG.14. As apparent from the comparison with the IGBT 20 shown in FIG. 13,an IGBT 21 shown in FIG. 14 comprises an n-type barrier layer 71 formedto reach the region deeper than the bottom surfaces of the trenches TRa,TRd. By forming the n-type barrier layer 71 so that the bottom surfacethereof is deeper than that of the trench in this manner, the positivehole does not flow in the interface portion with the oxide film, as isdescribed in the above third embodiment. The problem that theaccumulated amount of the positive holes drops by the surfacerecombination can also be solved and the on-resistance can further bereduced.

[0083] (11) Eleventh Embodiment

[0084]FIG. 15 is a sectional view showing the schematic constitution ofan eleventh embodiment of the semiconductor device according to thepresent invention. As apparent from the comparison with FIG. 28, thecharacteristics of an IGBT 22 shown in the figure lie in that, in thedummy trenches TRd1 to TRd3 which do not contact the current passage,the distance Wa between the active trench TRa1 (or TRa2) contacting thecurrent path, and the dummy trench TRd1 (or TRd3) positioned adjacent tothe active trench TRa1 (or TRa2) is set to be shorter than the distanceWd between the dummy trenches TRd1 and TRd2 (or between TRd3 and TRd2)not contacting the current path.

[0085] When the distance between the trenches is shortened, the electricfield of the region between the trenches is weakened. Therefore, thecarriers accumulated in the n⁻-type base layer 42 do not easily reachthe side walls of the trenches TRa1, TRa2, TRd1, and TRd3. This canprevent the carrier recombination in the surfaces of the trenches TRa1,TRa2, TRd1, and TRd3, and the carrier concentration in the n⁻-type baselayer 42 can be raised. As a result, the conductivity loss of the IGBT22 is reduced.

[0086] Moreover, the gate-collector capacitance is reduced, therebycontrollability of the IGBT 22 at the turn-on period is enhanced andstability at the turn-off period is further enhanced.

[0087] (12) Twelfth Embodiment

[0088]FIG. 16 is a sectional view showing the schematic constitution ofa twelfth embodiment of the semiconductor device according to thepresent invention. An IGBT 24 shown in the figure is different from theIGBT 22 shown in FIG. 15 in that the n-type barrier layer 70 isinserted/disposed between the n⁻-type base layer 42 and the p-typecontact layer 50. When the n-type barrier layer 70 is inserted/disposedin this manner, the resistance further increases in discharging thepositive hole to the emitter electrode 58 from the n⁻-type base layer42. As a result, since the accumulated amount of the positive holes canbe increased, the-conductive loss can further be reduced. Also in thepresent embodiment, the impurity concentration of the n-type barrierlayer 70 is higher than that of the n⁻-type base layer 42 at least inthe vicinity of the interface between the n-type barrier layer 70 andthe n⁻-type base layer 42. Furthermore, in the IGBT 24 of the presentembodiment, in order to prevent the breakdown voltage from beingdeteriorated, the distance between the active trenches is preferably 2μm or less as is described in the second embodiment.

[0089] A modification example of the present embodiment is shown in FIG.17. As apparent from the comparison with the IGBT 24 shown in FIG. 16,an IGBT 25 shown in FIG. 17 comprises the n-type barrier layer 71 formedto reach the region deeper than the bottom surfaces of trenches TRa,TRd. Since the n-type barrier layer is thus formed so that the bottomsurface thereof is deeper than that of the trench, the positive holedoes not flow in the interface portion with the oxide film. The problemthat the accumulated amount of the positive holes drops by the surfacerecombination can also be solved and the on-resistance can further bereduced, as is described above in the third embodiment.

[0090] (13) Thirteenth Embodiment

[0091]FIG. 18 is a sectional view showing the schematic constitution ofa thirteenth embodiment of the semiconductor device according to thepresent invention. An IGBT 26 shown in the figure is different from theIGBT 10 shown in FIG. 27 in that the IGBT 26 further comprises a p-typediverter layer 74 which is disposed in a surface portion of the deviceon an emitter side and in which the electrons are not injected. Theemitter electrode 58 is also disposed on the p-type diverter layer 74,and the p-type diverter layer 74 is directly connected to the emitterelectrode 58. It is to be noted that in the present embodiment theemitter electrode 58 contacting the n⁺-type source layer 48 is connectedto the emitter electrode 58 contacting the p-type diverter layer 74 by awiring 94. However, in the present invention, the arrangement of theemitter electrode is not limited to that in this embodiment. Forexample, as in an IGBT 27 shown in FIG. 19, an emitter electrode 78 iscontinuously formed to extend to the surface of the p-type diverterlayer 74 from the surface of the n⁺-type source layer 48 via the regionon an insulating film 92 of the trench disposed adjacent to the p-typediverter layer 74, thereby the wiring 94 can be omitted. Suchconstitution of the emitter electrode is in common applicable to thedevices in fourteenth through eighteenth embodiments described later.

[0092] The p-type diverter layer 74 disposed in this manner enhances thedestruction tolerance of the device since the positive hole isdischarged from the p-type diverter layer 74 at the turn-off. However,in an on-state, there is a problem that the on-resistance rises becausethe positive hole is not sufficiently accumulated due to the presence ofthe p-type diverter layer 74. To solve the problem, a structure has beenproposed in which a resistor or a diode is inserted between the emitterelectrode 58 and the p-type diverter layer 74 instead of directconnection of the emitter electrode to the p-type diverter layer (B. J.Baliga, “Trench-IGBTs with Integrated Diverter Structures”, Proceedingsof 1995 ISPSD, pp. 201, 1995). However, when the emitter electrode 58 isnot directly connected to the p-type diverter layer 74 there is also aproblem that the destruction tolerance is not enhanced because it isdifficult to discharge the positive hole at the turn-off.

[0093] As described above, in the IGBT 26 of the present embodiment, thep-type diverter layer 74 is directly connected to the emitter electrode58. Therefore, the destruction tolerance at the turn-off is enhanced. Onthe other hand, the discharge of the positive hole in the on-state canbe prevented by applying the gate voltage to deplete the p-type diverterlayer 74. This point is explained in more detail with reference to FIGS.20A and 20B. In the on-state, as shown in FIG. 20A, the p-type diverterlayer 74 is depleted since the gate voltage in the positive direction isapplied to the emitter electrode 58. When an impurity concentration Ndivand width Wdiv of the p-type diverter layer 74 are appropriatelyadjusted to completely deplete the p-type diverter layer 74, thepositive hole running toward the emitter electrode 58 is accumulated inthe n⁻-type base layer 42 without flowing into the p-type diverter layer74. Therefore, the on-resistance of the IGBT 26 can be reduced. At theturn-off, as shown in FIG. 20B, the gate voltage in a negative directionis applied to the emitter electrode 58, then a p-type accumulation layer84 appears in a trench side-wall portion of the p-type diverter layer74, and the discharge of the positive hole is promoted. As a result, thedestruction tolerance of the IGBT 26 is enhanced.

[0094] (14) Fourteenth Embodiment

[0095]FIG. 21 is a sectional view showing the schematic constitution ofa fourteenth embodiment of the semiconductor device according to thepresent invention. An IGBT 28 shown in the figure is different from theIGBT 26 shown in FIG. 18 in that the IGBT 28 comprises a punch throughstructure in which an n-type buffer layer 66 between the p⁺-type emitterlayer 44 and the n⁻-type base layer 42 is further included. The otherconstitution of the IGBT 28 is substantially the same as that of theIGBT 26 shown in FIG. 18.

[0096] (15) Fifteenth Embodiment

[0097]FIG. 22 is a sectional view showing the schematic constitution ofa fifteenth embodiment of the semiconductor device according to thepresent invention. In an IGBT 30 of the present embodiment, the diverterstructure shown in FIG. 18 is realized by a horizontal IGBT. Even inthis horizontal structure, the function/effect similar to that of thethirteenth embodiment can be obtained by the p-type diverter layer 74.

[0098] (16) Sixteenth Embodiment

[0099]FIG. 23 is a sectional view showing the schematic constitution ofa sixteenth embodiment of the semiconductor device according to thepresent invention. An IGBT 32 shown in the figure is different from theIGBT 30 shown in FIG. 22 in the punch through structure furtherincluding the n-type buffer layer 66 between the p⁺-type emitter layer44 and n⁻-type base layer 42. The other constitution of the IGBT 32 issubstantially the same as that of the IGBT 30 of FIG. 22.

[0100] (17) Seventeenth Embodiment

[0101]FIG. 24 is a sectional view showing the schematic constitution ofa seventeenth embodiment of the semiconductor device according to thepresent invention. As apparent from the comparison with FIG. 18, thecharacteristics of an IGBT 34 of the present embodiment lie in astructure further including an n-type barrier layer 80 disposed betweenthe n⁻-type base layer 42 and the p-type diverter layer 74. This n-typebarrier layer 80 further inhibits the positive hole from coming off inthe on-state, and an accumulation effect increases. On the other hand,at the turn-off, a p-type inversion layer is formed in the vicinity of atrench side wall of the n-type barrier layer 80. Accordingly, since thedischarge resistance of the positive hole lowers, a high destructiontolerance is maintained. It is to be noted that the width of the n-typebarrier layer 80 is preferably 2 μm or less as described in the secondembodiment.

[0102] (18) Eighteenth Embodiment

[0103]FIG. 25 is a sectional view showing the schematic constitution ofan eighteenth embodiment of the semiconductor device according to thepresent invention. An IGBT 36 shown in the figure is different from theIGBT 34 shown in FIG. 24 in that an n-type barrier layer 82 is alsodisposed in the cell including an MOS channel. The n-type barrier layer82 can further reduce the on-resistance of the IGBT 36.

[0104] (19) Nineteenth Embodiment

[0105]FIG. 26 is a sectional view showing the schematic constitution ofa nineteenth embodiment of the semiconductor device according to thepresent invention. An IGBT 38 shown in the figure is different from theIGBT 26 shown in FIG. 18 in that the n-type barrier layer 82 is disposedin the cell including the MOS channel. Even when the n-type barrierlayer is disposed only in this channel cell, the on-resistance of theIGBT 38 can be reduced.

[0106] The embodiments of the present invention have been describedabove, but the present invention is not limited to the above-describedembodiments, and can variously be changed and applied within the scopeand the spirit of the invention. For example, the cell arrangement shownin the perspective view of FIG. 8 or the plane view of FIG. 9 or 10 canalso be applied to the ninth through eighteenth embodiments.

[0107] The eighteen embodiments of the present invention have beendescribed, but by arbitrarily combining these embodiments together, thesemiconductor device can be realized in which the on-resistance isfurther low and the destruction tolerance is further high.

What is claimed is:
 1. A semiconductor device comprising: a base layerof a first conductivity type; a barrier layer of a first conductivitytype formed on the base layer; a trench formed from the surface of saidbarrier layer to such a depth as to reach a region in the vicinity of aninterface between said barrier layer and the base layer; a gateelectrode formed in the trench via a gate insulating film; a contactlayer of a second conductivity type selectively formed in a surfaceportion of said barrier layer; a source layer of the first conductivitytype selectively formed in the surface portion of said barrier layer soas to contact the contact layer and a side wall of the gate insulatingfilm in the trench; and a first main electrode formed so as to contactthe contact layer and the source layer.
 2. The semiconductor deviceaccording to claim 1, wherein a region between the trenches includes anactive region for a current path, the active region having a width of 2μm or less.
 3. The semiconductor device according to claim 1, wherein animpurity concentration of said barrier layer is higher than that of thebase layer at least in the vicinity of the interface with the baselayer.
 4. The semiconductor device according to claim 1, wherein theregion between the trenches includes a dummy region other than theactive region.
 5. The semiconductor device according to claim 4, whichfurther comprises an insulating film which is disposed on the contactlayer and the source layer in the dummy region and which electricallydisconnects the first main electrode from the dummy region.
 6. Asemiconductor device comprising: a base layer of a first conductivitytype; a barrier layer of the first conductivity type formed above thebase layer; a trench formed from the surface of the barrier layer tosuch a depth as to reach a region in the vicinity of an interfacebetween the barrier layer and the base layer; a gate electrode formed inthe trench via a gate insulating film; a contact layer of a secondconductivity type selectively formed in a surface portion of the barrierlayer; a source layer of the first conductivity type selectively formedin the surface portion of the barrier layer so as to contact a side wallof the gate insulating film in the trench and the contact layer; a welllayer of the second conductivity type formed between the contact layerand the source layer, and the barrier layer; and a first main electrodeformed so as to contact the contact layer and the source layer, whereinthe region between the trenches includes a dummy region having norelation to the operation of the device other than an active region fora current path.
 7. The semiconductor device according to claim 6, whichfurther comprises an insulating film which is disposed on the contactlayer and the source layer in the dummy region and which electricallydisconnects the first main electrode from the dummy region.
 8. Thesemiconductor device according to claim 6, wherein assuming that a totalsum of impurity densities in the region of the barrier layer between thetrenches is Qn, said Qn has a relation of the following equation:Qn≧2×10¹² cm⁻².
 9. The semiconductor device according to claim 6,wherein the active region between the trenches has a width of 2 μm orless.
 10. A semiconductor device comprising: a base layer of a firstconductivity type; a barrier layer of the first conductivity type formedon the base layer; a well layer of a second conductivity type formed onsaid barrier layer; a trench formed from the surface of the well layerto such a depth as to reach a region in the vicinity of a junctionsurface between the barrier layer and the base layer; a gate electrodeformed in the trench via a gate insulating film; a contact layer of thesecond conductivity type selectively formed in a surface portion of thewell layer; a source layer of the first conductivity type selectivelyformed in the surface portion of the well layer so as to contact a sidewall of the gate insulating film in the trench and the contact layer;and a first main electrode formed so as to contact the contact layer andthe source layer, wherein assuming that a total sum of impuritydensities in the region of said barrier layer between the trenches isQn, said Qn has a relation of the following equation: Qn≧2×10¹² cm⁻².11. The semiconductor device according to claim 10, wherein a regionbetween the trenches includes an active region for a current path, theactive region having a width of 2 μm or less.
 12. The semiconductordevice according to claim 10, wherein the contact layer and the sourcelayer are formed in a region between the trenches so as to bealternately disposed in a direction along the region between thetrenches.
 13. The semiconductor device according to claim 10, whereinthe source layer is formed around the contact layer, and cells arearranged so as to form a matrix in a plane view.
 14. The semiconductordevice according to claim 10, wherein cells are arranged so as to form aplurality of columns in parallel with each other and at the same pitchalong an arbitrary direction in a plane view, and a position of one endof the cell in an arbitrary column deviates in the arbitrary directionfrom that of the corresponding position of one end of the cell in theadjacent column.
 15. The semiconductor device according to claim 10,which further comprises: an emitter layer of the second conductivitytype formed on the surface of the base layer on a side opposite to aside on which the first main electrode is formed; and a second mainelectrode formed on the emitter layer and electrically connected to theemitter layer.
 16. The semiconductor device according to claim 10, whichfurther comprises: an emitter layer of the second conductivity typeformed on the surface of the base layer on the same side as that of thefirst main electrode; and a second main electrode formed on the emitterlayer and electrically connected to the emitter layer.
 17. Thesemiconductor device according to claim 15, which further comprises abuffer layer of the first conductivity type formed between the emitterlayer and the base layer.
 18. A semiconductor device comprising: a baselayer of a first conductivity type; a well layer of a secondconductivity type formed on the base layer; an active trench formed fromthe surface of the well layer to such a depth as to reach the inside ofthe base layer so as to sandwich an active region to form a current pathin the well layer; a dummy trench formed in the region excluding theactive region of the well layer from the surface of the well layer tosuch a depth as to reach the inside of the base layer; a gate electrodeformed in the active trench via a gate insulating film; a dummyelectrode formed in the dummy trench via the gate insulating film; asource layer of the first conductivity type selectively formed in asurface portion of the active region of the well layer so as to contacta side wall of the gate insulating film in the active trench; and afirst main electrode formed so as to contact at least the well layer andthe source layer, wherein the dummy electrode in the dummy trenchdisposed adjacent to the active trench is electrically connected to thegate electrode, and the dummy electrode other than that of the dummytrench disposed adjacent to the active trench is electrically connectedto the first main electrode.
 19. The semiconductor device according toclaim 18, wherein the active region for a current path has a width of 2μm or less.
 20. The semiconductor device according to claim 18, whichfurther comprises a barrier layer of the first conductivity type formedbetween the base layer and the well layer.
 21. The semiconductor deviceaccording to claim 20, wherein an impurity concentration of the barrierlayer is higher than that of the base layer at least in the vicinity ofthe interface with the base layer.
 22. The semiconductor deviceaccording to claim 20, wherein the barrier layer is formed so as toreach a region deeper than the bottom surface of the active trench andthe bottom surface of the dummy trench.
 23. The semiconductor deviceaccording to claim 18, wherein a contact portion of the well layercontacting the first main electrode and the source layer are formed inthe region between the active trenches so as to be alternately arrangedin a direction along the active trench.
 24. The semiconductor deviceaccording to claim 18, wherein the source layer is formed around thecontacting portion of the well layer contacting the first main electrodelayer, and cells are arranged so as to form a matrix in a plane view.25. The semiconductor device according to claim 18, wherein cells arearranged so as to form a plurality of columns in parallel with eachother and at the same pitch along an arbitrary direction in a planeview, and a position of one end of the cell in an arbitrary columndeviates in the arbitrary direction from that of the correspondingposition of one end of the cell in the adjacent column.
 26. Thesemiconductor device according to claim 18, which further comprises: anemitter layer of the second conductivity type formed on the surface ofthe base layer on a side opposite to a side on which the first mainelectrode is formed; and a second main electrode formed on the emitterlayer and electrically connected to the emitter layer.
 27. Thesemiconductor device according to claim 18, which further comprises: anemitter layer of the second conductivity type formed on the surface ofthe base layer on the same side as that of the first main electrode; anda second main electrode formed on the emitter layer and electricallyconnected to the emitter layer.
 28. The semiconductor device accordingto claim 26, which further comprises a buffer layer of the firstconductivity type formed between the emitter layer and the base layer.29. A semiconductor device comprising: a base layer of a firstconductivity type; a well layer of a second conductivity type formed onthe base layer; an active trench formed from the surface of the welllayer to such a depth as to reach the inside of the base layer so as tosandwich an active region for a current path in the well layer; a dummytrench formed in the region excluding the active region of the welllayer from the surface of the well layer to such a depth as to reach theinside of the base layer; a gate electrode formed in the active trenchvia a first gate insulating film; a dummy electrode formed in the dummytrench via a second gate insulating film; a source layer of the firstconductivity type selectively formed in a surface portion of the welllayer in the active region so as to contact a side wall of the gateinsulating film in the active trench; and a first main electrode formedso as to contact the well layer and the source layer, wherein a distancebetween the dummy trench disposed adjacent to the active trench, and theactive trench is shorter than that between the dummy trenches.
 30. Thesemiconductor device according to claim 29, wherein the active regionfor a current path has a width of 2 μm or less.
 31. The semiconductordevice according to claim 29, which further comprises a barrier layer ofthe first conductivity type formed between the base layer and the welllayer.
 32. The semiconductor device according to claim 31, wherein animpurity concentration of the barrier layer is higher than that of thebase layer at least in the vicinity of the interface with the baselayer.
 33. The semiconductor device according to claim 31, wherein thebarrier layer is formed so as to reach a region deeper than the bottomsurface of the active trench and the bottom surface of the dummy trench.34. A semiconductor device comprising: a base layer of a firstconductivity type; a well layer of a second conductivity typeselectively formed on an active region for a current path of the baselayer; a diverter layer of the second conductivity type selectivelyformed in a region of the base layer excluding the active region; afirst trench formed from the surface of the well layer to such a depthas to reach the inside of the base layer; a second trench formed fromthe surface of the diverter layer to such a depth as to reach the insideof the base layer; gate electrodes formed in the first and secondtrenches via insulating films; a source layer of the first conductivitytype selectively formed in a surface portion of the active region of thewell layer so as to contact a side wall of the gate insulating film inthe first trench,; and a first main electrode electrically connected tothe well layer, the source layer and the diverter layer.
 35. Thesemiconductor device according to claim 34, which further comprises afirst barrier layer of the first conductivity type formed between thediverter layer and the base layer so as to have an impurityconcentration higher than that of the base layer.
 36. The semiconductordevice according to claim 35, wherein said first barrier layer betweenthe first and second trenches has a width of 2 μm or less.
 37. Thesemiconductor device according to claim 35, which further comprises asecond barrier layer of the first conductivity type formed between thebase layer and the well layer so as to have an impurity concentrationwhich is higher than that of the base layer.
 38. The semiconductordevice according to claim 37, wherein said second barrier layer betweenthe first trenches has a width of 2 μm or less.
 39. The semiconductordevice according to claim 34, which further comprises a second barrierlayer of the first conductivity type formed between the base layer andthe well layer so as to have an impurity concentration which is higherthan that of the base layer.
 40. The semiconductor device according toclaim 39, wherein said second barrier layer between the first trencheshas a width of 2 μm or less.
 41. The semiconductor device according toclaim 34, wherein the source layer and a contact portion of the welllayer contacting the first main electrode are formed in the regionbetween the first trenches so as to be alternately arranged in adirection along the first trench.
 42. The semiconductor device accordingto claim 34, wherein the source layer is formed around the contactingportion of the well layer contacting the first main electrode layer, andcells are arranged so as to form a matrix in a plane view.
 43. Thesemiconductor device according to claim 34, wherein cells are arrangedso as to form a plurality of columns in parallel with each other and atthe same pitch along an arbitrary direction in a plane view, and aposition of one end of the cell in an arbitrary column deviates in thearbitrary direction from that of the corresponding position of one endof the cell in the adjacent column.
 44. The semiconductor deviceaccording to claim 34, which further comprises: an emitter layer of thesecond conductivity type formed on the surface of the base layer on aside opposite to a side on which the first main electrode is formed; anda second main electrode formed on the emitter layer and electricallyconnected to the emitter layer.
 45. The semiconductor device accordingto claim 34, which further comprises: an emitter layer of the secondconductivity type formed on the surface of the base layer on the sameside as that of the first main electrode; and a second main electrodeformed on the emitter layer and electrically connected to the emitterlayer.
 46. The semiconductor device according to claim 44, which furthercomprises a buffer layer of the first conductivity type formed betweenthe emitter layer and the base layer.